Nonvolatile memories using ferroelectric materials are broadly divided into two types: a capacitor-type, and a field effect transistor (FET)-type having a gate insulating film made of a ferroelectric film.
Capacitor-type nonvolatile ferroelectric memories are similar in structure to dynamic random access memories (DRAMs). Data in a capacitor-type nonvolatile ferroelectric memory is stored as a direction of polarization of the ferroelectric material caused by charges held in a ferroelectric capacitor. One polarization direction represents “0”, while the other polarization direction represents “1”. The polarization accumulated in the ferroelectric capacitor is coupled to charges induced by the upper and lower electrodes thereof, and therefore, does not dissipate when the voltage is cut off. However, when the data is read, the stored polarization is destroyed, so that the data is lost. In this technique, therefore, an operation for rewriting the data is needed. As a result, polarization reversal repeatedly occurs due to repetition of the rewrite operation performed after each read operation, leading to polarization fatigue. In addition, in this structure, since polarization charges are read by a sense amplifier, the amount of charges (typically 100 fC) equal to or larger than the sense limit of the sense amplifier is required. The amount of polarization charges per unit area of a ferroelectric material is material-specific. Hence, the electrode area required is constant as long as the same material is used, no matter how much a memory cell is miniaturized. It is therefore difficult to reduce the capacitor size in direct proportion to the miniaturization of process rules, and capacitor-type ferroelectric memories are thus unsuitable for an increase in capacity.
In contrast to this, in FET-type ferroelectric memories, data is read by detecting the conductive state of a channel which varies depending on the direction of polarization of a ferroelectric film. This allows non-destructive reading of data. Also, the amplitude of an output voltage can be increased through the amplifying operation of a FET. Therefore, FET-type ferroelectric memories can be miniaturized in accordance with the scaling law. A FET-type transistor has conventionally been proposed in which a ferroelectric film serving as a gate insulating film is formed on a silicon substrate serving as a channel. This structure is called a Metal-Ferroelectric-Semiconductor (MFS) FET.
In a memory cell array in which FET-type ferroelectric memories are arranged in a matrix with rows and columns, binary data is written into a ferroelectric memory by applying a voltage pulse between a gate electrode connected to a word line of a selected memory cell and a source electrode connected to a source line of the selected memory cell. In this case, however, a voltage is also applied to other memory cells which are connected to the word line and the source line of the selected memory cell and which are not to be accessed, resulting in erroneous writing of data, which is so-called “write disturbance”. Therefore, typically, a selection switch including, for example, a Metal-Insulator-Semiconductor FET (MISFET) is interposed between the word line and the gate electrode and/or between the source line and the source electrode, thereby preventing the write disturbance (see, for example, Japanese Unexamined Patent Application Publication No. H05-205487).